2(Intel中国研究中 心 编译组,北 京 100080) Hiding Memory Access Latency in Software Pipelining

Abstract: Software pipelining tries to improve the performance of a loop by overlapping the execution of several successive iterations. As processor gets much higher speed, the memory access latency becomes a bottleneck that restricts higher performance. Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency. This paper presents a foresighted latency modulo scheduling (FLMS) algorithm which determines the latency of load instructions according to the feature of the loop. Experimental results show that FLMS decreases the stall time and improves the performance of programs. Key words: software pipeline; modulo scheduling; memory access latency; FLMS (foresighted latency modulo scheduling) 摘 要: 软件流水是一种重要的指令调度技术,它通过同时执行来自不同循环体的指令来加快循环的执行 速 度.随着处理机运行速度的逐渐提高,存储访问延迟成为性能提高的瓶颈.为了减轻存储系统影响,软件流水结合 了一些存储优化技术,通过隐藏存储延迟来提高性能.提出了一种延迟可预测的模调度算法(foresighted latenc