Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches

Modern processors and compilers hide long memory latencies through non-blocking loads or explicit software prefetching instructions. Unfortunately, each mechanism has potential drawbacks. Non-blocking loads can signifi-cantly increase register pressure by extending the lifetimes of loads. Software prefetching increases the number of memory instructions in the loop body. For a loop whose exe-cution time is bound by the number of loads/stores that can be issued per cycle, software prefetching exacerbates this problem and increases the number of idle computational cy-cles in loops. In this paper, we show how compiler and architecture support for combining a load and a prefetch into one in-struction, called a prefetching load, can give lower regis-ter pressure like software prefetching and lower load/store-unit requirements like non-blocking loads. On a set of 106 Fortran loops we show that prefetching loads obtain a speedup of 1.07–1.53 over using just non-blocking loads and a speedup of 1.04–1.08 over using software prefetching. In addition, prefetching loads reduced floating-point regis-ter pressure by as much as a factor of 0.4 and integer regis-ter pressure by as much as a factor of 0.8 over non-blocking loads. Integer register pressure was also reduced by a fac-tor of 0.97 over software prefetching, while floating-point register pressure was increased by a factor of 1.02 versus software prefetching in the worst case.