The PC-set method and the parallel technique are two methods for performing compiled unit-delay simulation. The PC-set method analyzes the network, determines the set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on the concept of parallel fault simulation, is faster and generates less code than the PC-method, but is is less flexible. Benchmark comparisons with interpreted event-driven simulation show a factor of 4 improvement for the PC-set method and a factor of ten improvement for the parallel technique
Parallel CAD programs have been extensively reported in the literature. Unfortunately, they are not ...
In this paper, we describe distributed algorithms for combinational fault simulation assuming the cl...
technical reportEmpirical performance evaluations of parallel, discrete event simulation algorithms ...
The PC-set method and the parallel technique are two methods for generating compiled unit-delay simu...
The PC-set method and the parallel technique are two methods for generating compiled unit-delay simu...
The Inversion Algorithm is an event driven algorithm whose performance meets or exceeds that of Leve...
By introducing physically motivated time delays, simulation models can be partitioned into decoupled...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...
A parallel transient simulation technique for multiphysics circuits is presented. The technique deve...
Global virtual time (GVT) is used in parallel discrete event simulations to reclaim memory, commit o...
As the speed increase of single-core processors keeps declining, it is important to adapt simulation...
Simulation has become indispensable in the process of designing, verifying, and testing complex digi...
[[abstract]]Circuit simulation is a very time-consuming and numerically intensive application, espec...
This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled S...
Most experimental studies of the performance of parallel simulation protocols use speedup or number ...
Parallel CAD programs have been extensively reported in the literature. Unfortunately, they are not ...
In this paper, we describe distributed algorithms for combinational fault simulation assuming the cl...
technical reportEmpirical performance evaluations of parallel, discrete event simulation algorithms ...
The PC-set method and the parallel technique are two methods for generating compiled unit-delay simu...
The PC-set method and the parallel technique are two methods for generating compiled unit-delay simu...
The Inversion Algorithm is an event driven algorithm whose performance meets or exceeds that of Leve...
By introducing physically motivated time delays, simulation models can be partitioned into decoupled...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...
A parallel transient simulation technique for multiphysics circuits is presented. The technique deve...
Global virtual time (GVT) is used in parallel discrete event simulations to reclaim memory, commit o...
As the speed increase of single-core processors keeps declining, it is important to adapt simulation...
Simulation has become indispensable in the process of designing, verifying, and testing complex digi...
[[abstract]]Circuit simulation is a very time-consuming and numerically intensive application, espec...
This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled S...
Most experimental studies of the performance of parallel simulation protocols use speedup or number ...
Parallel CAD programs have been extensively reported in the literature. Unfortunately, they are not ...
In this paper, we describe distributed algorithms for combinational fault simulation assuming the cl...
technical reportEmpirical performance evaluations of parallel, discrete event simulation algorithms ...