Profiling Interrupt Handler Performance through Kernel Instrumentation

As a result of technology trends towards multi-gigahertz processors, the I/O system is becoming a critical bottle-neck for many applications. Interrupts are a major as-pect of most device drivers. Characterizing interrupt per-formance and its relation to architectural trends is impor-tant for understanding and improving I/O subsystem per-formance. Kernel instrumentation in combination with per-formance counters is able to overcome the limitations of microbenchmarks when measuring interrupts. A compar-ative analysis of a range of IA-32 based systems reveals that interrupt handler code exhibits only a low degree of instruction-level parallelism. Consequently, the trend to-wards deeper processor pipelines and smaller caches to maximize clock frequency can be detrimental to interrupt handling performance. 1