Test-pattern grading and pattern selection for small-delay defects

Timing-related defects are becoming increasingly impor-tant in nanometer technology designs. Small delay vari-ations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can po-tentially cause timing failures in a design, thereby lead-ing to quality and reliability concerns. We present a test-grading technique to leverage the method of output devi-ations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and it excites a larger number of long paths compared to pre-viously proposed timing-aware ATPG methods. We show that, for the same pattern count, the selected patterns are more effective than timing-aware ATPG for detecting small delay defects caused by resistive shorts, resistive opens, and process variations.