Abstract — This paper introduces a transformational de-sign method which can be used to map code written in a high level source language, like C, to a coarse grain reconfig-urable architecture. The source code is first translated into a Control Dataflow graph (CDFG), which is minimized using a set of behaviour preserving transformations such as de-pendency analysis, common subexpression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture. I
The first step in high level synthesis consists of translating a behavioral specification into its c...
Application-specific Instruction set extension to the computational capabilities of a processor prov...
Abstract Dataflow programs are widely used. Each program is a directed graph where nodes are comput...
This paper introduces a transformational design method which can be used to map code written in ahhi...
This paper presents an overview of a tool chain to support a transformational design methodology. Th...
This paper introduces a method which can be used to map applications written in a high level source ...
This paper introduces a method which can be used to map applications written in a high level source ...
This paper presents a method to automatically generate a Control Data Flow Graph (CDFG) from C/C++ s...
An architecture for a hand-held multimedia device requires components that are energy-efficient, fle...
In this paper we present a coarse grain CDFG (Control/Data Flow Graph) model suitable for hardware/s...
International audienceIn the approaching era of IoT, flexible and low power accelerators have become...
This paper describes a systematic method and an experi-mental software system for high-level transfo...
Morpheus promotes the transparent use of heterogeneous reconfigurable resources in system on chip. G...
. A structuring algorithm for arbitrary control flow graphs is presented. Graphs are structured into...
functional programming with dataflow evaluation, making it possible to write interactive programs in...
The first step in high level synthesis consists of translating a behavioral specification into its c...
Application-specific Instruction set extension to the computational capabilities of a processor prov...
Abstract Dataflow programs are widely used. Each program is a directed graph where nodes are comput...
This paper introduces a transformational design method which can be used to map code written in ahhi...
This paper presents an overview of a tool chain to support a transformational design methodology. Th...
This paper introduces a method which can be used to map applications written in a high level source ...
This paper introduces a method which can be used to map applications written in a high level source ...
This paper presents a method to automatically generate a Control Data Flow Graph (CDFG) from C/C++ s...
An architecture for a hand-held multimedia device requires components that are energy-efficient, fle...
In this paper we present a coarse grain CDFG (Control/Data Flow Graph) model suitable for hardware/s...
International audienceIn the approaching era of IoT, flexible and low power accelerators have become...
This paper describes a systematic method and an experi-mental software system for high-level transfo...
Morpheus promotes the transparent use of heterogeneous reconfigurable resources in system on chip. G...
. A structuring algorithm for arbitrary control flow graphs is presented. Graphs are structured into...
functional programming with dataflow evaluation, making it possible to write interactive programs in...
The first step in high level synthesis consists of translating a behavioral specification into its c...
Application-specific Instruction set extension to the computational capabilities of a processor prov...
Abstract Dataflow programs are widely used. Each program is a directed graph where nodes are comput...