This paper introduces a transformational design method which can be used to map code written in ahhigh level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Datafow graph (CDFG), which is minimized using a set of behaviour preserving transformations such as dependency analysis, common subexpression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture
This paper describes a framework supporting the automatic composition of reconfigurable overlays lai...
This paper presents various novel techniques for improving coarse-grained reconfigurable architectur...
Abstract — Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attent...
Abstract — This paper introduces a transformational de-sign method which can be used to map code wri...
This paper presents an overview of a tool chain to support a transformational design methodology. Th...
This paper introduces a method which can be used to map applications written in a high level source ...
This paper introduces a method which can be used to map applications written in a high level source ...
An architecture for a hand-held multimedia device requires components that are energy-efficient, fle...
This paper presents a method to automatically generate a Control Data Flow Graph (CDFG) from C/C++ s...
International audienceIn the approaching era of IoT, flexible and low power accelerators have become...
In this paper we present a coarse grain CDFG (Control/Data Flow Graph) model suitable for hardware/s...
Morpheus promotes the transparent use of heterogeneous reconfigurable resources in system on chip. G...
Today the most commonly used system architectures in data processing can be divided into three categ...
Coarse-grained reconfigurable architectures (CGRAs) have been well-researched and shown to be partic...
The availability of high-level design entry tooling is crucial for the viability of any reconfigurab...
This paper describes a framework supporting the automatic composition of reconfigurable overlays lai...
This paper presents various novel techniques for improving coarse-grained reconfigurable architectur...
Abstract — Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attent...
Abstract — This paper introduces a transformational de-sign method which can be used to map code wri...
This paper presents an overview of a tool chain to support a transformational design methodology. Th...
This paper introduces a method which can be used to map applications written in a high level source ...
This paper introduces a method which can be used to map applications written in a high level source ...
An architecture for a hand-held multimedia device requires components that are energy-efficient, fle...
This paper presents a method to automatically generate a Control Data Flow Graph (CDFG) from C/C++ s...
International audienceIn the approaching era of IoT, flexible and low power accelerators have become...
In this paper we present a coarse grain CDFG (Control/Data Flow Graph) model suitable for hardware/s...
Morpheus promotes the transparent use of heterogeneous reconfigurable resources in system on chip. G...
Today the most commonly used system architectures in data processing can be divided into three categ...
Coarse-grained reconfigurable architectures (CGRAs) have been well-researched and shown to be partic...
The availability of high-level design entry tooling is crucial for the viability of any reconfigurab...
This paper describes a framework supporting the automatic composition of reconfigurable overlays lai...
This paper presents various novel techniques for improving coarse-grained reconfigurable architectur...
Abstract — Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attent...