A high performance application representation for reconfigurable systems

Modern reconfigurable computing systems feature pow-erful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarchies. Mapping applications to these com-plex systems requires a representation that allows both hardware and software synthesis. Additionally, this repre-sentation must enable optimizations that exploit fine and coarse grained parallelism in order to effectively utilize the performance of the underlying reconfigurable archi-tecture. Our work explores a representation based on the program dependence graph (PDG) incorporated with the static single-assignment (SSA) for synthesis to high per-formance reconfigurable devices. The PDG effectively de-scribes control dependencies, while SSA yields precise data dependencies. When used together, these two representa-tions provide a powerful, synthesizable form that exploits both fine and coarse grained parallelism. Compared to other commonly used representations for reconfigurable systems, the PDG+SSA form creates faster execution time, while using similar area. 1