This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems running an operating system with preemptive multitasking. Existing SPM allocation schemes do not support multiple tasks or only a fixed number of processes that are known at compile time. These schemes rely on algorithms that select code depending on the size of the SPM. In contemporary portable devices, however, processes are created and terminated on demand and the SPM is shared among them. We introduce a dynamic scratchpad memory code alloca-tion technique for code that supports dynamically created processes. At runtime, an SPM manager (SPMM) loads code pages of the running applications into the SPM on de-mand. It supports different shari...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
Portable embedded systems require diligence in manag-ing their energy consumption. Thus, power efcie...
Abstract—We propose a code scratchpad memory (SPM) management technique with demand paging for embed...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
CASES 2010 : International Conference on Compilers, Architecture, and Synthesis for Embedded System...
In this paper, we propose a methodology for energy reduction and performance improvement. The target...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
Software-controlled scratchpad memory is increasingly employed in embedded systems as it offers bett...
Abstract—A method to both reduce energy and improve perfor-mance in a processor-based embedded syste...
In this paper, we propose a fully automatic dynamic scratch-pad memory (SPM) management technique fo...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
Portable embedded systems require diligence in manag-ing their energy consumption. Thus, power efcie...
Abstract—We propose a code scratchpad memory (SPM) management technique with demand paging for embed...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
CASES 2010 : International Conference on Compilers, Architecture, and Synthesis for Embedded System...
In this paper, we propose a methodology for energy reduction and performance improvement. The target...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
Software-controlled scratchpad memory is increasingly employed in embedded systems as it offers bett...
Abstract—A method to both reduce energy and improve perfor-mance in a processor-based embedded syste...
In this paper, we propose a fully automatic dynamic scratch-pad memory (SPM) management technique fo...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...