Recpu: a parallel and pipelined architecture for regular expression matching

Text pattern matching is one of the main and most compu-tation intensive parts of systems such as Network Intrusion Detection Systems and DNA Sequencing Matching. Soft-ware solutions to this are available but often they do not satisfy the requirements in terms of performance. This pa-per presents a new hardware approach for regular expression matching: ReCPU. The proposed solution is a parallel and pipelined architecture able to deal with the common regular expression semantics. This implementation based on sev-eral parallel units achieves a throughput of more than one character per clock cycle (maximum performance of current proposed solution) requiring just O(n) memory locations (where n is the length of the regular expression). Perfor-mance has been evaluated synthesizing the VHDL descrip-tion. Area and time constraints have been analyzed. Exper-imental results are obtained simulating the architecture. 1