A time slice based scheduler model for system level design

Efficient evaluation of design choices, in terms of selec-tion of algorithms to be implemented as hardware or soft-ware, and finding an optimal hw/sw design mix is an impor-tant requirement in the design flow of Embedded Systems. Time-to-market, faster upgradability and flexibility are some of the driving points to put increasing amounts of function-ality as software executed on general purpose processing el-ements. In this scenario, dividing a monolithic task into mul-tiple interacting tasks, and scheduling them on limited pro-cessing elements has become very important for a system de-signer. This paper presents an approach to model time-slice based task schedulers in the designs where the performance estimate of hardware and software models is less than time-slice accurate. The approach aims to increase the simula-tion efficiency of designs modeled at system level. We used Metropolis [1] as our codesign environment. 1