We propose a low overhead, on-line memory monitor-ing scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the number of hits from increasing the cache size or hit-rates as a function of cache size. Using the counters, we describe a scheme that enables an accurate estimate of the isolated miss-rates of each process as a function of cache size under the standard LRU replacement policy. This in-formation can be used to schedule jobs or to partition the cache to minimize the overall miss-rate. The data collected by the monitors can also be used by an analytical model of cache and memory behavior to produce a more accurate overall miss-rate for the collection of processes shari...
An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order micropr...
In this paper we present a method for determining the cache performance of the loop nests in a progr...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates t...
Scientific and technological advances in the area of integrated circuits have allowed the performanc...
Techniques for analyzing and improving memory referencing behavior continue to be important for achi...
Modern processors incorporate several performance monitoring units, which can be used to count event...
Abstract. We develop a new metric for job scheduling that in-cludes the effects of memory contention...
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase th...
Memory contention is one of the largest sources of inter-core interference in statically partitioned...
Classic cache replacement policies assume that miss costs are uniform. However, the correlation betw...
Chip Multiprocessors (CMPs) have become the architecture of choice for high-performance general-purp...
Miss Rate Curves (MRCs) for main memory have been proposed as a representation of memory utilization...
The increasing number of processors in today's many-core architectures has lead to new issues regard...
We develop a reuse distance/stack distance based analytical modeling framework for efficient, online...
An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order micropr...
In this paper we present a method for determining the cache performance of the loop nests in a progr...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates t...
Scientific and technological advances in the area of integrated circuits have allowed the performanc...
Techniques for analyzing and improving memory referencing behavior continue to be important for achi...
Modern processors incorporate several performance monitoring units, which can be used to count event...
Abstract. We develop a new metric for job scheduling that in-cludes the effects of memory contention...
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase th...
Memory contention is one of the largest sources of inter-core interference in statically partitioned...
Classic cache replacement policies assume that miss costs are uniform. However, the correlation betw...
Chip Multiprocessors (CMPs) have become the architecture of choice for high-performance general-purp...
Miss Rate Curves (MRCs) for main memory have been proposed as a representation of memory utilization...
The increasing number of processors in today's many-core architectures has lead to new issues regard...
We develop a reuse distance/stack distance based analytical modeling framework for efficient, online...
An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order micropr...
In this paper we present a method for determining the cache performance of the loop nests in a progr...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...