NXP Semiconductors

In a multiprocessor system on chip private caches introduce the cache coherence problem; because processors can have an incoherent view on the shared memory because of stale data in their caches. Cache coherence protocols have been designed to ensure a coherent view on the background memory. Both hardware as well as software solutions have been introduced in the past, and hardware solutions can be roughly divided in two approaches. The first is a snooping-based approach, which relies on global visibility of writes and write atomicity, and is therefore difficult to apply efficiently in combination with a network-on-chip. The second is a directory-based approach, which has as a major drawback the increased memory access latency. This increase is a result of consulting the directory upon memory accesses. Software cache coherence protocols have the potential to ensure cache coherence with-out requiring global visibility of writes and without increasing the memory access latency. Therefore software cache coherence protocols can be a candidate to be used in combination with a network-on-chip. We propose a software cache coherence protocol that can be applied in a heterogeneou