1 A New Bit-Level Algorithm for General Purpose Median Filtering

Median filtering has proved an effective way to remove impulse noise while preserving rapid signal changes. A classic general purpose Median filter is based on a ‘Bubble Sort ’ approach. In this paper, we present a novel bit-level algorithm which is readily scalable and very compact. The basis of the algorithm is similar to that of Quicksort, and is based on a ‘Bit Voter ’ (BV) block. The paper also extends the basic BV algorithm to include Weighted Median and Ranked Order Median filtering. The median finding unit, whose inputs are the N pixel values to sort, has a O(N) hardware complexity compared to a O(N2) complexity for an equivalent unit using Bubble sort. The novel algorithm has been implemented on a Xilinx Spartan XCS30XL-4 FPGA chip. For comparison purposes, we also present an FPGA implementation of an existing ‘Triple Input Sorter ’ based algorithm (TIS) which is an optimised version of the Bubble sort algorithm for the special case of a 3x3 window size. The BV’s median finding unit occupies 15 Configurable Logic Blocks (CLBs) only whereas TIS occupies 60 CLBs. For PAL video (720x576 images of 8-bit/pixel), comparative timings show that BV can operate at 26 frames per second (fps), while TIS can achieve 33 fps. Thus, both algorithms can achieve real time performance, and BV is the more compact.