Median Filter with FPGA applications

Abstract — The selective median filter is a mixed filter which removes spike noise (or an impulse noise) from a noisy image while preserving sharp edges. For this purpose we can use a double derivative filter or Laplace filter which acts as a noise detector. If it is found noisy then we apply a general median filter. The median filter technique, the eight direct neighbours and centre point of a sliding 3-by-3 array are examined. A selective median filter which consumes less power can be designed and different logics for majority bit evaluation can be applied and simulate in VHDL. Different majority bit calculation method can be implement and the result sorting circuit can be analyze for power analysis and can be implement in FPGA like hardware