Challenges of the Mask Manufacturing Approaching Physical Limits

Over the past 25 years, following the International Technology Roadmap for Semiconductors1, the main feature size of integrated circuits has decreased from approximately 3µm to 70nm. With feature sizes well below the exposure wavelength of the stepper, resolution enhancement features such as serifs, scatter-bars, and hammer heads are added to the mask design. Given a 4:1 reduction from mask to wafer, the resolution enhancement features, such as scatter bars, are roughly the same size as main features on the wafer. Recently, with the reduction of mask feature size, mask manufacturing technology faces several problems in satisfying customer needs for resolution, CD uniformity, and CD linearity. The problems result, in part, as the legacy of material and process choices made in the early days of mask making. For example, the use of chrome as an absorber was suitable material choice for wet etch binary mask processes, but this material is now seen as problematic current dry etch process. Another general source of problems for the mask industry is its small size relative to wafer manufacturing. As a result, vendors focus material and equipment development efforts on wafer, and then make adaptations to fit mask making requirements. Nowadays the patterns of high end lithographic masks are written by variable shaped beam 50k