Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Sub-sequent references to words within the same cache line re-sult in cache hits. Although this approach benefits from spa-tial locality, less than half of the data brought into the cache gets used before eviction. The unused portion of the cache line negatively impacts performance by wasting bandwidth and polluting the cache by replacing potentially useful data that would otherwise remain in the cache. This paper describes an alternative approach to exploit spatial locality available in data caches. On a cache miss, our mechanism, called Spatial Footprint Predictor (SFP), predicts which portions of a cache block will get used ...
Since the introduction of cache memories in computer architecture, techniques to improve the data lo...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
The speed of processors increases much faster than the memory access time. This makes memory accesse...
Applications often under-utilize cache space and there are no software locality optimization techniq...
Recent research suggests that there are large variations in a cache's spatial usage, both within and...
This paper proposes an optimization by an alternative approach to memory mapping. Caches with low se...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
Over the past decades, core speeds have been improving at a much higher rate than memory bandwidth. ...
This paper studies the theory of caching and temporal and spatial locality. We show the following re...
Locality, characterized by data reuses, determines caching performance. Reuse distance (i.e. LRU st...
Abstract – Here we present an architecture for improving data cache miss rate. Our enhancement seeks...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
Commercial link : http://www.springerlink.de/ ALCHEMY/http://www.springer.comCache memories were inv...
The purpose of this paper is to reevaluate the performance of the Split Temporal/Spatial (STS) cache...
The locality of a program may be quantified by the data footprint over a time period or by the miss ...
Since the introduction of cache memories in computer architecture, techniques to improve the data lo...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
The speed of processors increases much faster than the memory access time. This makes memory accesse...
Applications often under-utilize cache space and there are no software locality optimization techniq...
Recent research suggests that there are large variations in a cache's spatial usage, both within and...
This paper proposes an optimization by an alternative approach to memory mapping. Caches with low se...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
Over the past decades, core speeds have been improving at a much higher rate than memory bandwidth. ...
This paper studies the theory of caching and temporal and spatial locality. We show the following re...
Locality, characterized by data reuses, determines caching performance. Reuse distance (i.e. LRU st...
Abstract – Here we present an architecture for improving data cache miss rate. Our enhancement seeks...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
Commercial link : http://www.springerlink.de/ ALCHEMY/http://www.springer.comCache memories were inv...
The purpose of this paper is to reevaluate the performance of the Split Temporal/Spatial (STS) cache...
The locality of a program may be quantified by the data footprint over a time period or by the miss ...
Since the introduction of cache memories in computer architecture, techniques to improve the data lo...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
The speed of processors increases much faster than the memory access time. This makes memory accesse...