Performance Estimation of Embedded Software with Instruction Cache Modeling

Embedded systems generally interact with the outside world. Thus, some real-time constraints may be imposed on the system design. Verification of these constraints re-quires computing a tight upper bound on the worst case execution time (WCET) of a hardware/software system. The problem of bounding WCET is particularly difficult on modern processors, which use cache-based memory sys-tems that vary memory access time significantly. This must be accurately modeled in order to tightly bound WCET. Existing approaches either search all possible pro-gram paths, an intractable problem, or they use pes-simistic assumptions to limit the search space. In this pa-per we present a far more effective and accurate method for modeling instruction cache activity and computing a tight bound on WCET. It is implemented in the program cinderella. We present some preliminary results of us-ing this tool on sample embedded programs.