PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking ∗

This paper describes an approximate approach for combinational equivalence checking. We propose an architecture such that a virtually-zero aliasing rate is obtained in a single-pass probability calculation. Fur-thermore, the aliasing rate can be easily configured in various precision by designers. We conduct experiments on a set of ISCAS’85 benchmarks. Experimental results show that with virtually-zero aliasing rate, for example, 10−74, our approach is more efficient than those exact approaches. Traditionally, logic verification is carried out by pat-tern simulation. However, to exhaustively simulate all possible patterns is infeasible for practical designs wit