Abstract—Architectures in which multicore chips are augmented with graphics processing units (GPUs) have great potential in many domains in which computationally intensive real-time workloads must be supported. How-ever, unlike standard CPUs, GPUs are treated as I/O devices and require the use of interrupts to facilitate communication with CPUs. Given their disruptive nature, interrupts must be dealt with carefully in real-time systems. With GPU-driven interrupts, such disruptiveness is further compounded by the closed-source nature of GPU drivers. In this paper, such problems are considered and a solution is presented in the form of an extension to LITMUSRT called klitirqd. The design of klitirqd targets systems with multiple CPUs and GPUs...
In this paper we describe a new, low-overhead technique for manipulating processor interrupt state i...
Interrupt-based programming is widely used for interfacing a processor with peripherals and allowing...
In heterogeneous CPU+GPU SoCs where a single DRAM is shared between both devices, concurrent memory ...
This paper describes GPUSync, which is a framework for managing graphics processing units (GPUs) in ...
Abstract—Graphics processing units (GPUs) are increasingly being used for general purpose parallel c...
In order to satisfy timing constraints, modern real-time applications require massively parallel acc...
In this paper we analyze the traditional model of interrupt management and its incapacity to incorpo...
Graphic Processing Units (GPUs) are currently widely used in High Performance Computing (HPC) applic...
Cyber-physical systems (CPS) integrate sensing, computing, communication and actuation capabilities ...
We present GPU-to-CPU callbacks, a new mechanism and abstraction for GPUs that offers them more inde...
The fact that graphics processors (GPUs) are today’s most powerful computational hardware for the do...
Embedded systems can fail to operate correctly due to interrupt overload: starvation caused by too m...
Motivated by computational capacity and power efficiency, techniques for integrating graphics proces...
ManuscriptWhile developing embedded and real-time systems, it is usually necessary to write code tha...
Abstract- Interrupt-based programming is widely used for interfacing a processor with peripherals an...
In this paper we describe a new, low-overhead technique for manipulating processor interrupt state i...
Interrupt-based programming is widely used for interfacing a processor with peripherals and allowing...
In heterogeneous CPU+GPU SoCs where a single DRAM is shared between both devices, concurrent memory ...
This paper describes GPUSync, which is a framework for managing graphics processing units (GPUs) in ...
Abstract—Graphics processing units (GPUs) are increasingly being used for general purpose parallel c...
In order to satisfy timing constraints, modern real-time applications require massively parallel acc...
In this paper we analyze the traditional model of interrupt management and its incapacity to incorpo...
Graphic Processing Units (GPUs) are currently widely used in High Performance Computing (HPC) applic...
Cyber-physical systems (CPS) integrate sensing, computing, communication and actuation capabilities ...
We present GPU-to-CPU callbacks, a new mechanism and abstraction for GPUs that offers them more inde...
The fact that graphics processors (GPUs) are today’s most powerful computational hardware for the do...
Embedded systems can fail to operate correctly due to interrupt overload: starvation caused by too m...
Motivated by computational capacity and power efficiency, techniques for integrating graphics proces...
ManuscriptWhile developing embedded and real-time systems, it is usually necessary to write code tha...
Abstract- Interrupt-based programming is widely used for interfacing a processor with peripherals an...
In this paper we describe a new, low-overhead technique for manipulating processor interrupt state i...
Interrupt-based programming is widely used for interfacing a processor with peripherals and allowing...
In heterogeneous CPU+GPU SoCs where a single DRAM is shared between both devices, concurrent memory ...