Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards

This is the author’s version of the work. The definitive work was published in Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), 2011. Abstract. In the last decade, there has been a dramatic growth in re-search and development of massively parallel commodity graphics hard-ware both in academia and industry. Graphics card architectures pro-vide an optimal platform for parallel execution of many number crunch-ing loop programs from fields like image processing or linear algebra. However, it is hard to efficiently map such algorithms to the graphics hardware even with detailed insight into the architecture. This paper presents a multiresolution image processing algorithm and shows the ef-ficient mapping of this type of algorithms to graphics hardware as well as double buffering concepts to hide memory transfers. Furthermore, the impact of execution configuration is illustrated and a method is proposed to determine offline the best configuration. Using CUDA as program-ming model, it is demonstrated that the image processing algorithm i