Memory system energy: influence of hardware-software optimizations

Memory system usually consumes a signicant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the in-teraction of two hardware cache optimization mechanisms (block buering and sub-banking) and three widely used compiler optimization techniques (linear loop transforma-tion, loop tiling, and loop unrolling). Our results show that the pure hardware optimizations (eight block buers and four sub-banks in a 4K, 2-way cache) provided up to 4 % en-ergy saving, with an average saving of 2 % across all bench-marks. In contrast, the pure software optimization approach that uses all three compiler optimizations, provided at least 23 % energy saving, with an average of 62%. However, a closer observation reveals that hardware optimization be-comes more critical for on-chip cache energy reduction when executing optimized codes. 1