Available online xxxx

interferences between tasks in the worst case. This is very complex with variable latency hardware, such time and energy consumption by delivering data and instructions with an average latency of a few processor cycles. Unfortunately, tion belongs to a cached and locked memory line and not on the pre-vious accesses. In this paper, we focus on the instruction fetch path and analyze several configurations of the memory architecture shown in Fig. 1. It consists of a line buffer (LB) and a lockable instruction cache (i-cache). The i-cache retains the fixed subset of instruction lines pre-viously loaded by system software at task switches. It does not need fine-grained locking, but whole cache-locking. The LB has the size of a cache line and acts as a single-line cache memory regarding the tag, access latency and refill latency. The only differ-ence with a conventional cache is that it prevents exploiting an