Optimistic intra-transaction parallelism on chip multiprocessors

With the advent of chip multiprocessors, ex-ploiting intra-transaction parallelism is an at-tractive way of improving transaction perfor-mance. However, exploiting intra-transaction parallelism in existing database systems is difficult, for two reasons: first, significant changes are required to avoid races or con-flicts within the DBMS, and second, adding threads to transactions requires a high level of sophistication from transaction program-mers. In this paper we show how dividing a transaction into speculative threads solves both problems—it minimizes the changes re-quired to the DBMS, and the details of par-allelization are hidden from the transaction programmer. Our technique requires a lim-ited number of small, localized changes to a subset of the low-level data structures in the DBMS. Through this method of parallelizing transactions we can dramatically improve per-formance: on a simulated 4-processor chip-multiprocessor, we improve the response time by 36–74 % for three of the five TPC-C trans-actions.