Abstract. The motivation of this work is to ask whether Transactional Memory (TM) and Thread-Level Speculation (TLS), two prominent con-currency paradigms usually considered separately, can be combined into a hybrid approach that extracts untapped parallelism and speed-up from common programs. We show that the answer is positive by describing an algorithm, called TLSTM, that leverages an existing TM with TLS capabilities. We also show that our approach is able to achieve up to a 48 % increase in throughput over the base TM, on read dominated workloads of long transactions in a multi-threaded application, among other results.
With the advent of chip multiprocessors, exploiting intratransaction parallelism in database systems...
This paper presents thread-level transactional memory (TTM), a memory system interface that separat...
There has been a flurry of recent work on the design of high performance software and hybrid hardwar...
The traditional single-core processors are being replaced by chip multiprocessors (CMPs) where sever...
Exploiting thread-level parallelism has become a part of mainstream programming in recent years. Man...
Computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase...
Chip Multithreading (CMT) processors promise to deliver higher performance by running more than one ...
TPC-C, subepochs Thread level speculation (TLS) has proven to be a promising method of extracting pa...
The current trend towardmulticore architectures has placed great pressure on programmers and compile...
The current trend toward chip multiprocessor architectures has placed great pressure on programmers ...
While architects understand how to build cost-effective parallel machines across a wide spectrum of ...
While architects understandhow to build cost-effective parallel machines across a wide spectrum of m...
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from bo...
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from bo...
Transactional Memory (TM) stands as a powerful paradigm for manipulating shared data in concurrent a...
With the advent of chip multiprocessors, exploiting intratransaction parallelism in database systems...
This paper presents thread-level transactional memory (TTM), a memory system interface that separat...
There has been a flurry of recent work on the design of high performance software and hybrid hardwar...
The traditional single-core processors are being replaced by chip multiprocessors (CMPs) where sever...
Exploiting thread-level parallelism has become a part of mainstream programming in recent years. Man...
Computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase...
Chip Multithreading (CMT) processors promise to deliver higher performance by running more than one ...
TPC-C, subepochs Thread level speculation (TLS) has proven to be a promising method of extracting pa...
The current trend towardmulticore architectures has placed great pressure on programmers and compile...
The current trend toward chip multiprocessor architectures has placed great pressure on programmers ...
While architects understand how to build cost-effective parallel machines across a wide spectrum of ...
While architects understandhow to build cost-effective parallel machines across a wide spectrum of m...
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from bo...
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from bo...
Transactional Memory (TM) stands as a powerful paradigm for manipulating shared data in concurrent a...
With the advent of chip multiprocessors, exploiting intratransaction parallelism in database systems...
This paper presents thread-level transactional memory (TTM), a memory system interface that separat...
There has been a flurry of recent work on the design of high performance software and hybrid hardwar...