A Design Methodology for Secured ICs Using Dynamic Current Mode Logic

Abstract. This paper considers the security of Integrated Circuits (IC’s) against power analysis attacks. We present a methodology for the se-cure design of cryptographic IC’s and apply it to the Dynamic Current Mode Logic (DyCML). For this purpose, we first propose to use a Binary Decision Diagram (BDD) approach in order to predict the power con-sumption of certain critical gates of an encryption algorithm. Then, we validate our model using SPICE simulations. Based on these predictions, we demonstrate that it is only possible to mount power analysis attacks against certain instances of DyCML circuits. We also illustrate that the attack efficiency depends on the quality of the power consumption mod-els, themselves depending on the representation chosen for the targeted boolean function. Relying on these simulation results, we finally propose a complete methodology to (1) find the most secure instance of a boolean function and (2) derive secure ICs from these optimized structures