Design-for-debug for post-silicon validation: Can high-level descriptions help?

Post-silicon validation is an essential step in the de-sign flow, which is needed to demonstrate that the imple-mented circuit meets its intended behavior. Due to lack of in-system controllability and observability, design-for-debug hardware is employed to aid post-silicon validation. A number of solutions have been proposed to implement the design-for-debug hardware, as well as to analyze the debug data that is acquired. Although the design entry is done at the register-transfer level, the existing approaches to aid post-silicon validation rely primarily on the information ex-tracted from the gate level circuit descriptions. We antic-ipate that, as the design complexity continues to grow, ex-tracting and processing circuit information at this level will become increasingly difficult. In this paper, we briefly sum-marize the known art and discuss some possible directions of investigation that can utilize high-level circuit descrip-tions to augment the existing solutions. 1