Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis

Assertion Based Design, and more specifically, Assertion Based Verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are mainly targeted at functional verification during the design and verification phases. In this paper, we concentrate on the use of assertions in post-fabrication silicon debug. We develop tools that effi-ciently generate the checkers from assertions, for their inclu-sion in the debug phase. We also detail how a checker gen-erator can be used as a means of circuit design for certain portions of self test circuits, and more generally the design of monitoring circuits. Efficient subset partitioning of check-ers for a dedicated fixed-size reprogrammable logic area is developed for efficient use of dedicated debug hardware. 1