A Study of P and N-Doping in the Thick Gate of a 100V UMOS Device for HCI Improvement

[[abstract]]The UMOS field effect transistor or UMOSFET is a form of vertical or “trench” style structure used for MOS transistors. This form of semiconductor “trench” or vertical semiconductor technology offers significant advantages in term of speed and lowering the ON resistance. As a result, many manufacturers of semiconductor electronics components offer a vertical form of structure for their transistor. The UMOSFETs are able to provide a useful function in many relatively high-power applications, both in power supplies and RF power transistors. Trench MOS devices offer electronics designers a choice of lower heat dissipation for the same size chip, a higher current handling capability from the same sized chip, or a smaller chip with the same dissipation. In UMOS, the source is at the top of the device, and the drain is at the bottom. Instead of flowing horizontally as in the standard FET, current in this device flows vertically. The device uses two connections for the source and accordingly there is a much large area through which the current can flow. This reduces the ON resistance of the device allowing it to handle much higher powers than conventional FETs. Lower Ron is an important factor for devices for applications in automotive industry. The Trench MOS technology provides a significant improvement over previous power MOS technologies. This new form of power MOSFET is an electronics component which uses a new structure to provide a more direct and hence more efficient path for the current flow within the semiconductor device. Process and device simulators serve as a valuable tool for optimizing the design of process technologies and it is necessary to understand the accurate profile of the device. In this thesis, we will discuss an innovative n-channel U-shaped trench-gated MOSFETs (n-UMOS-FETs) device structure with breakdown voltage over 100V and low Ron, which is robust to hot carrier injection (HCI). The purpose of this work is to show the effect of p-type and n-type doping in the thick gate oxide and poly-gate region on HCI reliability