Design of nonvolatile on-chip memory using spin torque devices

The demand for fast, large-capacity, energy-efficient, and cost-effective memory in computing systems has led to intense research and development effort to find a memory technology that can present all the desired attributes of today\u27s memories: speed of Static Random Access Memory (SRAM), density of Dynamic RAM (DRAM), and non-volatility of Flash. Spin-Transfer Torque Magnetic RAM (STT-MRAM) has emerged as the leading candidate due to its non-volatility, superior scalability, and good compatibility with CMOS fabrication process. However, high write-current requirement in standard 1 Transistor -1 MTJ (1T1R) STT-MRAM presents a key challenge toward the achievement of low write-power, high integration density, and unlimited write endurance. Moreover, the shared read and write path severely limits the memory design space. The focus of this research is two-fold: 1) Investigation of the design issues in current MRAM technology and proposals of device- and circuit-level design solutions. First, we analyze asymmetric write currents in standard 1T-1R STT-MRAMs, and identify a potential for write power reduction. To that effect, we propose low-power circuit design techniques to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Next, we propose a novel MRAM device structure that exploits spin Hall effect (SHE) to create a differential memory cell for fast and energy-efficient memory applications. Then, we present new multi-level-cell design concepts for spin-orbit torque (SOT) MRAM to improve the integration density. 2) Investigation of spin-devices to implement specialized on-chip hardware, namely true random number generator, suitable for security and cryptography applications