On the impact of supply voltage variation on the statistical reliability of a Spin-transfer-torque MRAM (STT-MRAM)

The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) presents as a promising alternative to today embedded memories due to its reduced read/write latency and high integration capability. Today aggressive technology scaling requirements, affects also the STT-MRAM by means of fabrication induced process variability and aging phenomena. These issues make reliability prediction a major concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory. The reliability prediction is performed at cell level, accounting for fabrication induced variability and aging phenomena simultaneously affecting the nMOS and MTJ devices. In addition, the effect of supply voltage variation on the cell reliability is also studied. The results show that a negative variation of the supply voltage highly degrades the cell reliabilit