Characteristics and parameter extraction of Silicon-On-Insulator MOSFETS for analogue circuit modelling

The aims of the work presented in this thesis are twofold: to characterise the dynamic behaviour of SOI MOSFETs over a wide range of frequencies; and to develop accurate techniques for extracting physical parameters required for the compact modelling of parasitic effects in SOI MOSFETs, for application to analogue circuit design.Small-signal drain conductance techniques are developed as a useful tool for the analysis of the dynamic behaviour of SOI MOSFETs over a wide range of frequencies; these are particularly relevant to analogue applications, because the MOSFET output conductance is an important parameter in the design of amplifiers and other circuits. These small-signal measurements are then used to investigate dynamic floating body and self-heating effects, and to provide a basis for the development of new parameter extraction techniques.Novel parameter extraction techniques presented in this thesis include a technique to extract the partially depleted SOI film thicknesses, methods to characterise the physical elements contributing to floating body behaviour in partially depleted SOI MOSFETs, a technique to extract the thermal resistance and capacitance parameters required for the physical modelling of dynamic self-heating effects, and techniques for the characterisation of static and dynamic thermal coupling between MOSFETs in close proximity. These new parameter extraction techniques, together with well-known techniques developed for bulk MOSFETs, provide all elements required to compile a comprehensive parameter extraction methodology for the physically based, partially depleted SOI MOSFET model developed at Southampton University (STAG).Finally, the significance of self-heating and thermal coupling effects on the operation of several frequently used analogue circuits is investigated. The applications discussed are a 7-bit current steering D/A converter, current controlled ring oscillators and various current mirror layouts in a typical 0.7 μm PD SOI CMOS technology. It is shown that localised heating effects have a significant influence on the linearity of the D/A converter and the matching of the current mirrors, but are less important for the high frequency oscillator circuits.