Modified Input Scanning Method Used to 32 Bit X 32 Bit Multiprecision Multiplier

In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. Previous paper in used the PLL for the frequency division. If use the PLL for frequency division its hardware complexity increases .If frequency division is done by software using some frequency division method means hardware complexity is decrease and also speed is increases. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the user's requirements (e.g. throughput) a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency