With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely costeffective solution for leading edge applications. The original STAG2 model, developed at the University of Southampton, UK, was among the first compact circuit simulation models to specifically model the behaviour of Partially-Depleted (PD) SOI devices. STAG2 was a robust, surface-potential based compact model, employing closed-form equations to minimise simulation times for large circuits. It wa...
We present a new unified analytical front surface potential model. It is valid in all regions of ope...
Fully Depleted Silicon-On-Insulator is a promising technology but there were limitations in it due t...
This paper presents a compact model implemented in Verilog-A for partially depleted (PD) silicon-on-...
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have becom...
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constrai...
In this paper, the Southampton Thermal Analogue (STAG) compact model for partially depleted (PD) sil...
Abstract — This paper reports recent progress on partially depleted (PD) SOI modeling using a surfac...
A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device m...
Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is ...
A circuit simulation model is presented suitable for the design of analogue and digital SOS MOSFET i...
In this paper, we have developed a novel compact charge-conservative model for fully depleted silico...
In this thesis a circuit simulator model is developed, based on a detailed study of device physics o...
A new analytical model is presented for the threshold voltage of fully depleted silicon-on-insulator...
Abstract — SOI means Silicon on Insulator. This type of transistors has Silicon-Insulator-Silicon su...
International audienceAn analytical drain-current compact model for lightly doped short-channel ultr...
We present a new unified analytical front surface potential model. It is valid in all regions of ope...
Fully Depleted Silicon-On-Insulator is a promising technology but there were limitations in it due t...
This paper presents a compact model implemented in Verilog-A for partially depleted (PD) silicon-on-...
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have becom...
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constrai...
In this paper, the Southampton Thermal Analogue (STAG) compact model for partially depleted (PD) sil...
Abstract — This paper reports recent progress on partially depleted (PD) SOI modeling using a surfac...
A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device m...
Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is ...
A circuit simulation model is presented suitable for the design of analogue and digital SOS MOSFET i...
In this paper, we have developed a novel compact charge-conservative model for fully depleted silico...
In this thesis a circuit simulator model is developed, based on a detailed study of device physics o...
A new analytical model is presented for the threshold voltage of fully depleted silicon-on-insulator...
Abstract — SOI means Silicon on Insulator. This type of transistors has Silicon-Insulator-Silicon su...
International audienceAn analytical drain-current compact model for lightly doped short-channel ultr...
We present a new unified analytical front surface potential model. It is valid in all regions of ope...
Fully Depleted Silicon-On-Insulator is a promising technology but there were limitations in it due t...
This paper presents a compact model implemented in Verilog-A for partially depleted (PD) silicon-on-...