Reliability improvement in reconfigurable FPGAs

Séminaire des jeudis de la com' de l'équipe SCNUsually, there are two ways that a combinational logic function can be implemented in FPGAs, i) Multiplexer-based and ii) Memory-based (Look-Up Tables [LUT]). ARDyT CLE architecture plans to have LUT-based structure, as in the case of Xilinx Virtex architectures, due to the advantage of implementing maximum possible logic functions in it, when compared to multiplexer-based architectures. The content of LUT-SRAM cells are part of FPGA's configuration bitstream and they are protected using built-in configuration bitstream scheme. The focus here is to deal with the faults occurring in the multiplexers. It is very important to understand the fault models and their consequences before applying fault mitigation schemes to any given logic resource. As far as multiplexers are concerned, it does not contain any storage element to get affected by radiation-induced single event upsets and thereby to create a consequence of single-bit or multi-bit upsets. Faults in multiplexers are more of transient effects and circuit faults. The circuit level faults include radiation-induced stuck-at-faults and bridging faults. Unlike fabrication faults, the effect of these radiation induction faults could be temporary as well as permanent according to the nature and intensity of the radiation particle. Figure shown above demonstrates, how to check the 4:1 multiplexer with the 'Two-Rail Checker' circuit. The transistor pairs (Q17-Q18 and Q19-Q20) used in the checker circuit, are characterized by different aspect ratios to achieve different voltage thresholds VT1 and VT2. If the 'OUT' node is at an intermediate voltage, the checker circuit outputs E1 and E2 produce different voltage levels, if not, E1 and E2 are at same voltage level. The 'OUT' node is at intermediate voltage when there is a fault in the circuit. Hence it is interpreted as, in the absence of fault, output of the checker circuit E1 and E2 assume the value 11 or 00. If a fault occurs in the multiplexer, E1 and E2 shall assume the value 01 or 10. According to E1 and E2, the 'Error Evaluator' generates error status signal 'Err comp' to indicate the occurrence of fault in the combinational logic to the `reliable resource manager', to perform fault mitigation