A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such asmany general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycleMAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, aQCELPvocoder, and anMPEGvideo decoder. The effects ofCPUclock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.This study was supported by the Korea Science and Engineering Foundation (KOSEF) under grant no. 96-0102-04-01-3 and the academic research fund of the Ministry of Education, Republic of Korea, through Inter-University Semiconductor Research Center (ISRC 97-E-2101)