Effects of Silicon Variation on Nano-scale Solid-state Memories

This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.Ph