Fully-Depleted Silicon-On-Insulator (FD-SOI) wafers are promising substrates for new generations of CMOS transistors. A FD-SOI wafer consists of an ultrathin (~10 nm) silicon layer sitting on top of a buried oxide (BOx) layer itself on a thick (~750 µm) silicon handle wafer. Since final transistor characteristics dramatically fluctuate with thickness variations of the top layer, the capability of assessing and mastering thickness uniformity over a very large spatial bandwidth (from transistor to wafer scales, 10 nm - 300 mm) is a major challenge for this new application. In this work, a multi-scale metrology method, based on the use of the Power Spectral Density (PSD) functions allowing the treatment of data recorded from several experiment...