Hardware Accelerator of Inverse Discrete Cosine Transformation for JPEG Algorithms

Cilj ovog rada je korištenjem razvojne pločice ZedBoard koja je zasnovana na Xilinx Zynq porodici programirljivih SoC sklopova realizirati sklopovski ubrzivač za inverznu diskretnu kosinusnu transformaciju. U računarstvu postoje problemi koji nisu optimalni za rješavanje u potpunosti programski. Kao jedan takav algoritam čiji bi se dijelovi potencijalno mogli sklopovski ubrzati pokazuje se algoritam JPEG. JPEG je tako opisan u početnom poglavlju ovog rada, nakon čega su obavljena mjerenja vremena izvođenja JPEG dekodera. Kao najsporiji dio algoritma pokazala se IDCT funkcija koja će se zato pokušati sklopovski ubrzati. Za sklopovsku implementaciju IDCT funkcije korištena je Xilinx Zedboard razvojna pločica koja u svome središtu ima Zynq™-7000 AP SoC, koji pak svoju arhitekturu dijeli na programabilnu logiku i procesor. IDCT funkcija je tako implementirana u programabilnoj logici Zynq Soc-a. Nakon implementacije sklopovskog ubrzivača obavljena su mjerenja nad programskom verzijom IDCT-a i izvedenom sklopovskom te su rezultati uspoređeni. Kao rezultat ovog rada pretpostavka da je IDCT moguće ubrzati sklopovski se pokazala kao točna pošto je sama transformacija i više nego 3 puta ubrzana. Ali problem i na ovakvoj optimiziranoj konfiguraciji predstavlja prijenos podataka do sklopa s kojim se sklopovska izvedba znatno uspori. Kao posljedica toga sam prijenos i njegova optimizacija prelazi u središte razmatranja budućeg razvoja.The main goal of this paper is to implement hardware accelerator of Inverse Discrete Cosine Transformation for JPEG Algorithms by using Zedboard development board which is based on Xilinx Zynq family of programmable Soc portfolio. Often, there are problems in computer science which are not optimal to be fully solved in software. JPEG is one such algorithm whose parts could be faster if implemented in hardware. For that reason JPEG is described in first chapter of this paper after which time measuring for parts of JPEG decoder was made. IDCT is proven as the slowest part of JPEG decoder and for that reason it was implemented in hardware as a part of this paper. For hardware implementation Xilinx Zedboard development board was used, which operates on Zynq™-7000 AP SoC which has programmable logic and processor parts on it. IDCT function is implemented in programmable logic part of Zynq Soc. After implementing hardware accelerator times were measured for both hardware and software implementation and results were compared. As a result of this paper the assumption that IDCT can be improved by implementing it in hardware is proven right because the transformation is as much as 3 times faster. However, even on these kind of architecture the problem is data transfer which when included results in worse performance in hardware and this data transfer becomes the main point of further development