Development of Edge Detector Architecture on SoC

Computer vision applications –ranging from mobile phones to autonomous vehicle –require real-time processing with high speed operations and lower power consumption. We can solve this issue by designing embedded systems with different types of processors like microcontroller, Digital Signal Processor (DSP), or Field Programmable Gate Array (FPGA). The micro-controller/DSP-processor based designs employ a sequential computer architecture which may reduce its speed of operations. To alleviate this one may increase the clock speed but with a considerable amount of increase in power consumption. In this context, an FPGA based design can exploit the inherent parallel nature of an algorithm and employ different hardware blocks in concurrence. Thus, the overall operations are performed in less number of clock cycles and subsequently with lower power consumption. However, in some computer applications, parallelization of the algorithm is not always possible. In such cases, we need a combination of sequential and parallel computer architecture i.e. a System-on-Chip (SoC). The main aim of this dissertation is to develop image filter architecture on Zynq 7000 SoC platform. In this project hardware accelerator of Sobel, Prewitt filter algorithms are simulated and synthesized using HLS (High-Level Synthesis) tool. Vivado design suite is used to integrate all video processing related IP (Intellectual property) cores and user defined IP’s. Video stream pass through using AXI4 streaming design is developed and tested on ZC702 SoC board. This analysis and implementation may encourage and serve as a basic building block for several complex computer vision applications