On variability and reliability of CMOS and spin-based devices

The continuous demand for high performance applications and simultaneous lowering of power consumption and manufacturing cost is driving the transistor size to sub-50nm regime. Although, aggressive transistor scaling has resulted in increased integration density and improved device performance, it comes at the expense of increased variability such as random dopant fluctuations (RDF), line edge roughness (LER) and severe reliability issues such as negative bias temperature instability (NBTI), hot carrier injection (HCI) and time dependent dielectric breakdown (TDDB). Hence, in order to overcome the challenges posed by the variability and reliability issues, there is a need for accurate models that can capture these phenomena in a common framework. To that effect, we have developed physics-based 3-D analytical models that accurately estimate the distribution of transistor threshold voltage (Vth) for nanoscaled CMOS devices due to process variations. In addition, we have considered and investigated the correlation between RDF and NBTI, leading to proper estimation of transistor degradation in nano-scale devices. The random nature of the devices is modeled by introducing appropriate random variables and stochastic differential equations which provide the time-dependent Vth-distribution. We also propose a SPICE model which estimates the increase in the gate leakage current due to TDDB and the breakdown statistics of ultra thin-oxides. Thus, the performance of a circuit (i.e. delay, noise margin, and aging) can be accurately predicted under process variations. Interestingly, it is observed that the variability and reliability issues are also present in emerging technologies such as magnetic tunnel junctions (MTJs). MTJ is the key element in the design of spin-transfer torque magnetic random access memories (STT-MRAMs). We have developed a physics-based SPICE model for the simulation of circuits that use hybrid-MTJ/CMOS technology. Based on this model the variability issues of the STT-MRAM cell with one and two MTJs in the stack (or bits/cell) are investigated. Moreover, this framework is extended to capture the degradation of MTJs related to TDDB of the thin oxide (e.g. MgO). Using this model, we have estimated the time dependent degradation in the STT-MRAM\u27s critical performance parameters such as TMR, critical write current (JC) and lifetime (TLIFE )