True energy-performance analysis of the MTJ-based logicin-memory architecture (1-bit full adder

Abstract—The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient. Index Terms—Adders, complimentary metal–oxide– semiconductor (CMOS) digital integrated circuits, energy-delay tradeoff, magnetic tunnel junction (MTJ) logic, spin-transfer torque (STT) devices. I