Leakage in nanometer scale CMOS circuits

High leakage current in deep sub-micron regimes is a significant contributor to the power dissipation of CMOS circuits as the CMOS technology scales down. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications.. This paper explores transistor leakage mechanisms and device and circuit techniques to reduce leakage power consumption. For over 30 years CMOS devices have been continuously scaled to achieve higher density, better performance, and lower power consumption. With each technology generation, transistor delay times hav