Abstract — This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability, a parasitic bipolar model, and self-heating. A nonlinear body resistance is included for modeling body-contacted SOI devices. The PSP-SOI model has been extensively tested on several PD/SOI technologies. I
Abstract—This work describes an advanced physics-based com-pact MOSFET model (SP). Both the quasista...
An accurate submicrometer MOSFET device model for Silicon-On-Insulator (SOI) technology suitable for...
Investigations of floating body behaviour of partially depleted (PD) SOI MOSFETs have established th...
Body resistance Harmonic balance a b s t r a c t This paper reports recent progress in partially dep...
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have becom...
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constrai...
This paper describes a unified framework to model the floating-body effects of various SOI MOSFET op...
In this paper, the Southampton Thermal Analogue (STAG) compact model for partially depleted (PD) sil...
Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is ...
We present a new unified analytical front surface potential model. It is valid in all regions of ope...
This paper presents a surface-potential-based non-charge-sheet core model for long-channel fully dep...
A physically based analytical I-V model that includes self-heating effect (SHE) is presented for ful...
A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device m...
A compact terminal current/charge model for partially/dynamically/fully depleted (PD)/(DD)/(FD) doub...
This letter provides a viewpoint for the characterization of state-of-the-art thin film silicon-on-i...
Abstract—This work describes an advanced physics-based com-pact MOSFET model (SP). Both the quasista...
An accurate submicrometer MOSFET device model for Silicon-On-Insulator (SOI) technology suitable for...
Investigations of floating body behaviour of partially depleted (PD) SOI MOSFETs have established th...
Body resistance Harmonic balance a b s t r a c t This paper reports recent progress in partially dep...
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have becom...
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constrai...
This paper describes a unified framework to model the floating-body effects of various SOI MOSFET op...
In this paper, the Southampton Thermal Analogue (STAG) compact model for partially depleted (PD) sil...
Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is ...
We present a new unified analytical front surface potential model. It is valid in all regions of ope...
This paper presents a surface-potential-based non-charge-sheet core model for long-channel fully dep...
A physically based analytical I-V model that includes self-heating effect (SHE) is presented for ful...
A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device m...
A compact terminal current/charge model for partially/dynamically/fully depleted (PD)/(DD)/(FD) doub...
This letter provides a viewpoint for the characterization of state-of-the-art thin film silicon-on-i...
Abstract—This work describes an advanced physics-based com-pact MOSFET model (SP). Both the quasista...
An accurate submicrometer MOSFET device model for Silicon-On-Insulator (SOI) technology suitable for...
Investigations of floating body behaviour of partially depleted (PD) SOI MOSFETs have established th...