The Design and Realization of Depletion Mode MOSFET Devices

Our study involves the design, fabrication, and characterization of the basic depletion mode MOSFET devices on four-inch silicon wafers. The results of our study will include discussions of the following: 1) basic semiconductor device design and processing procedures using our laboratory facilities within the Department of Electrical and Computer Engineering at the Virginia Military Institute; 2) depletion MOSFET (D-MOS) technology, including device structure, design layout, fabrication procedures, and device characteristics (I-V and transfer characteristics); 3) the effect of different doping procedures on the performance characteristics of the D-MOS device; and 4) an evaluation of the performance characteristics of the D-MOS transistors that are fabricated in our laboratory. This study will provide valuable information to be applied in the future design and realization of digital logic gates that use these new transistor configurations as an alternative to previous designs