AVESTA SASAN

Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and output drivers, contribute a large fraction of the overall cache leakage. In addition, as technology migrates to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, indicating that leakage will be a major contributor to overall power consumption. This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processors on-chip caches by targeting leakage in cache peripheral circuits. At the circuit level, we propose a novel design with multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and wakeup delay. Architectural control is proposed to decide when and how to use these different low-leakage modes by utilizing cache miss information to guide its action. The control is based on simple state machines that do not impact area or power consumption and can thus be used even in resource-constrained processors. Experimental results indicate that the proposed techniques can keep the data cache peripherals in one of the low-power modes for more than 85 % of total execution time. The instruction cache is in one of the low power modes for an average of 50 % of the time. This translates to an average leakage power reduction of 50 % for DL1 and 30 % for IL1 in 65nm technology. The energy-delay product is reduced, on average, by up to 21%. Th