Abstract. This paper summarizes the results of evaluating several op-timizations targeted at reducing power consumption for ARM architec-ture within the GCC framework. The optimizations tried were off-line dynamic voltage scaling (DVS) and bit-switching minimization. Also, we have experienced with tunings of memory-related GCC optimizations.
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconduc...
This paper explores the limits of microprocessor power savings available via certain classes of arch...
This diploma thesis discusses the applicability of GCC optimization algorithms for the TI TMS320C6x ...
The demand for high-performance architectures and powerful battery-operated mobile devices has accen...
This project considered various sources of power consumption in general purpose high-performance and...
This paper studies the overall system power variations of two multi-core architectures, an 8-core In...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
Compile-time optimization of code can result in significant performance gains. The amount of these g...
Compile-time optimization of code can result in significant performance gains. The amount of these g...
Abstract—Optimizing for energy constraints is of critical importance due to the proliferation of bat...
AbstractModern compilers can work on many platforms and implement a lot of optimizations, which are ...
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Althou...
Abstract –How to evaluate computer’s performance is an important issue for engineers in the area of ...
The overhead in terms of code size, power consumption, and execution time caused by the use of preco...
Memory system usually consumes a significant amount of energy in many battery-operated devices. In t...
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconduc...
This paper explores the limits of microprocessor power savings available via certain classes of arch...
This diploma thesis discusses the applicability of GCC optimization algorithms for the TI TMS320C6x ...
The demand for high-performance architectures and powerful battery-operated mobile devices has accen...
This project considered various sources of power consumption in general purpose high-performance and...
This paper studies the overall system power variations of two multi-core architectures, an 8-core In...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
Compile-time optimization of code can result in significant performance gains. The amount of these g...
Compile-time optimization of code can result in significant performance gains. The amount of these g...
Abstract—Optimizing for energy constraints is of critical importance due to the proliferation of bat...
AbstractModern compilers can work on many platforms and implement a lot of optimizations, which are ...
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Althou...
Abstract –How to evaluate computer’s performance is an important issue for engineers in the area of ...
The overhead in terms of code size, power consumption, and execution time caused by the use of preco...
Memory system usually consumes a significant amount of energy in many battery-operated devices. In t...
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconduc...
This paper explores the limits of microprocessor power savings available via certain classes of arch...
This diploma thesis discusses the applicability of GCC optimization algorithms for the TI TMS320C6x ...