Worst-case execution time analysis for digital signal processors

We present ongoing work to develop a software tool for es-timating worst-case execution times for real-time, embed-ded programs. The tool applies static analysis to executable machine-code programs. Currently we mainly aim at sup-porting the TSC-21020E Digital Signal Processor, but the tool is designed to be easy to adapt to other target proces-sors as well. Contrary to most other WCET tools we attempt (whenever possible) automatic estimation of loop bounds. We also pro-vide a rich assertion language, which can be used to set bounds on loops that the tool itself cannot bound.