Cache Coherence Support for NonShared Bus Architecture on Heterogeneous MPSoCs

We propose two novel integration techniques | bypass and bookkeeping | in the memory controller to address the cache coherence compatibility issue of a non-shared bus heteroge-neous MPSoC. The bypass approach is an inexpensive and ecient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forward-ing trac oers an alternative for bandwidth-limited appli-cations. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution. Categories and Subject Descriptors C.3 [Computer Systems Organization]: Special-purpose and application-specic systems, Real-time and embedde