For the design of complex digital signal processing systems block diagram oriented synthesis of real time software for programmable target processors has become an important design aid The synthesis approach discussed in this paper is based on multirate block diagrams with scalable synchro nous data ow SSDF semantics For this class of data ow graphs we present scheduling techniques for optimum data memory compaction These techniques can be employed to map signals of a block diagram onto a minimum data me mory space In order to formalize the data memory com paction problem we rst derive appropriate implementa tion measures Based on these implementation measures it can be shown that optimum data memory compaction con sists of optimum s...
Complexities of applications implemented on embedded and programmable systems grow with the advances...
Abstract: Minimizing memory requirements for program and data are critical objectives when synthesiz...
We introduce a new approach to take into account the mem-ory architecture and the memory mapping in ...
There has been a proliferation of block-diagram environments for specifying and prototyping DSP sys...
There has been a proliferation of block-diagram environments for specifying and prototyping DSP sys-...
T his paper addresses trade-offs between the minimization of program memory and data memory requirem...
High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses s...
Achieving optimal throughput by extracting parallelism in behavioral synthesis often exaggerates mem...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
In this paper we address the problem of minimizing buffer storage requirement in constructing rate-o...
ISBN : 1-58113-853-9We introduce a new approach to take into account the memory architecture and the...
In the context of digital signal processing, synchronous data flow (SDF) graphs [12] are widely used...
In high level synthesis a data-flow graph (DFG) description of an algorithm is mapped onto a registe...
Complexities of applications implemented on embedded and programmable systems grow with the advances...
Abstract: Minimizing memory requirements for program and data are critical objectives when synthesiz...
We introduce a new approach to take into account the mem-ory architecture and the memory mapping in ...
There has been a proliferation of block-diagram environments for specifying and prototyping DSP sys...
There has been a proliferation of block-diagram environments for specifying and prototyping DSP sys-...
T his paper addresses trade-offs between the minimization of program memory and data memory requirem...
High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses s...
Achieving optimal throughput by extracting parallelism in behavioral synthesis often exaggerates mem...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
In this paper we address the problem of minimizing buffer storage requirement in constructing rate-o...
ISBN : 1-58113-853-9We introduce a new approach to take into account the memory architecture and the...
In the context of digital signal processing, synchronous data flow (SDF) graphs [12] are widely used...
In high level synthesis a data-flow graph (DFG) description of an algorithm is mapped onto a registe...
Complexities of applications implemented on embedded and programmable systems grow with the advances...
Abstract: Minimizing memory requirements for program and data are critical objectives when synthesiz...
We introduce a new approach to take into account the mem-ory architecture and the memory mapping in ...